View RC5050M_4578369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

electronics semiconductor division features programmable output from 1.3v to 3.5v 85% ef?iency typical 1% output accuracy oscillator frequency adjustable from 80khz to 1mhz on-chip power good and enable functions over-voltage protection foldback current limiting precision trimmed low tc voltage reference 20 pin soic package meets intel pentium ii speci?ations using minimum number of external components applications programmable power supply for pentium ii voltage regulator module (vrm) for pentium ii processors programmable step-down power supply description the rc5050 is a dc-dc controller ic which provides an accurate, programmable output for all pentium ii cpu appli- cations. the rc5050 uses a 5-bit d/a converter to program the output voltage from 1.3v to 3.5v. the rc5050 uses a high level of integration to deliver load currents in excess of 15a from a 5v source with minimal external circuitry. non- synchronous operation allows a low cost solution for most cpu power supply applications. the internal oscillator can be programmed from 80khz to 1mhz for additional ?xi- bility in choosing external components. an on-board preci- sion low tc reference achieves tight tolerance voltage regulation without expensive external components. the rc5050 also offers integrated functions including power good, output enable, over-voltage protection and current limiting. block diagram digital control + 1.24v reference 5-bit dac 65-5050-01 power good osc pwrgd vref vid0 vid1 vid2 vid4 vid3 enable + + + +5v vo rc5050 +12v rc5050 programmable dc-dc converter for low voltage microprocessors rev. 1.2.1 pentium is a registered trademark of intel corporation.
rc5050 product specification 2 pin assignments pin de nitions pin number pin name pin function description 1 cext oscillator capacitor connection . connecting an external capacitor to this pin sets the internal oscillator frequency. layout of this pin is critical to system performance. see application information for details. 2 enable output enable . open collector/ttl input. logic low will disable output. a 10k w internal pull-up resistor assures correct operation if pin is left unconnected. 3 pwrgd power good flag . open collector output will be at logic high under normal operation. logic low indicates output voltage is not within 12% of nominal. 4 ifb high side current feedback . pins 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. layout of these traces is critical to system performance. see application information for details. 5 vfb voltage feedback . pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. layout of this trace is critical to system performance. see application information for details. 6 vcca analog vcc . connect to system 5v supply and decouple to ground with 0.1 m f ceramic capacitor. 7 vccd digital vcc . connect to system 5v supply and decouple to ground with 4.7 m f tantalum capacitor. 8 vid4 vid4 input . a logic 1 on this open collector/ttl input will enable the vid3?id0 inputs to set the output from 2.1v to 3.5v, and a logic 0 on this pin will set the output from 1.3v to 2.05v, as shown in table 1. pullup resistors are internal to the controller. 9, 11 nc no internal connection . connection of these pins to system ground will improve the thermal dissipation characteristics of the package. 10 gndp power ground . return pin for high currents flowing in pins 12 and 13 (hidrv and vccqp). connect to low impedance ground. 12 hidrv fet driver output . connect this pin to the gates of n-channel mosfets m1 and m2 in figure 1. the trace from this pin to the mosfet gates should be < 0.5". 13 vccqp power vcc . this is the power supply for the fet driver. vccqp must be connected to a voltage of at least vcca + v gs,on (m1). see application information for details. 14 gndd digital ground . return path for digital logic. this pin should be connected to system ground to minimize ground loops. 15 gnda analog ground . return path for low power analog circuitry. connect to system ground to minimize ground loops. 16 vref reference voltage test point . this pin provides access to the dac output and should be decoupled to ground using a 0.1 m f capacitor. no load should be connected. 17?0 vid3 vid0 voltage identification (vid) code inputs . these open collector/ttl compatible inputs will program the output voltage over the ranges specified in table 1. pullup resistors are internal to the controller. 1 2 3 4 5 6 8 7 vid0 vid1 vid2 vid3 vref gnda vccqp gndd 20 19 18 17 16 15 13 9 12 10 11 14 cext enable pwrgd ifb vfb vcca vid4 vccd nc hidrv gndp nc 65-5050-02
product specification rc5050 3 absolute maxim um ratings operating conditions electrical characteristics (v cca , v ccd = 5v , v out = 2.8v , f osc = 300 khz, and t a = +25 c using figure 1, unless otherwise speci ed) the denotes speci cations which apply o v er the full oper ating temper ature r ange . notes: 1. steady state voltage regulation includes initial voltage setpoint, dc load regulation, output ripple/noise and temperature drift. 2. these specifications assume a minimum of 20, 1 m f ceramic capacitors are placed directly next to the cpu in order to provide adequate high-speed decoupling. for motherboard applications, the pcb layout must exhibit no more than 0.5m w parasitic resistance and 1nh parasitic inductance between the converter output and the cpu. supply voltages, v cca , v ccd , v ccqp 13v voltage identification code inputs, vid4-vid0 13v junction temperature, t j 150 c storage temperature -65 to 150 c lead soldering temperature, 10 seconds 300 c p arameter conditions min. t yp. max. units supply voltages, v cca and v ccd 4.5 5 7 v output driver supply, v ccqp 8.5 12 v input logic high 2.0 v input logic low 0.8 v pwrgd threshold logic high logic low 93 88 107 112 %v o %v o ambient operating temperature 0 70 c p arameter conditions min. t yp. max. units output voltage see table 1 1.3 3.5 v output current 13 a initial voltage setpoint i load = 0.8a 20 mv output temperature drift t a = 0 to 60 c +10 mv load regulation i lo ad = 0.8a to 13a -25 mv line regulation v in = 4.75 to 5.25v 2 mv output ripple 20mhz bw, i lo ad = 13a 11 mv output voltage regulation steady state 1 transient 2 v out = 2.8v, i load = 0.8 ?15a i lo ad = 0.8 to 14.2a, 30a/ m s 2.74 2.67 2.80 2.80 2.90 2.93 v v short circuit detect threshold 100 120 140 mv efficiency i lo ad = 13a, v out = 2.8v 80 85 % output driver rise and fall time see figure 2 50 ns turn-on response time i lo ad = 0 to 13a 10 ms oscillator range 80 300 1000 khz oscillator frequency c ext = 100 pf 270 300 330 khz max duty cycle pwm mode 90 95 %
rc5050 product specification 4 t ab le 1. output v olta g e pr ogramming codes note: 1. 0 = processor pin is tied to gnd 1 = processor pin is open. vid4 vid3 vid2 vid1 vid0 v out to cpu 0 1 1 1 1 1.30v 0 1 1 1 0 1.35v 0 1 1 0 1 1.40v 0 1 1 0 0 1.45v 0 1 0 1 1 1.50v 0 1 0 1 0 1.55v 0 1 0 0 1 1.60v 0 1 0 0 0 1.65v 0 0 1 1 1 1.70v 0 0 1 1 0 1.75v 0 0 1 0 1 1.80v 0 0 1 0 0 1.85v 0 0 0 1 1 1.90v 0 0 0 1 0 1.95v 0 0 0 0 1 2.00v 0 0 0 0 0 2.05v 1 1 1 1 1 no cpu 1 1 1 1 0 2.1v 1 1 1 0 1 2.2v 1 1 1 0 0 2.3v 1 1 0 1 1 2.4v 1 1 0 1 0 2.5v 1 1 0 0 1 2.6v 1 1 0 0 0 2.7v 1 0 1 1 1 2.8v 1 0 1 1 0 2.9v 1 0 1 0 1 3.0v 1 0 1 0 0 3.1v 1 0 0 1 1 3.2v 1 0 0 1 0 3.3v 1 0 0 0 1 3.4v 1 0 0 0 0 3.5v
product specification rc5050 5 t ypical operating characteristics (vcca, vccd = 5v , f osc = 280 khz, and t a = +25 c using circuit in figure 1, unless otherwise noted) efficiency vs. output current 65-5050-03 80.0 78.0 76.0 74.0 82.0 84.0 86.0 88.0 90.0 92.0 1 3 5 7 9 11 13 v out = 3.3v v out = 2.8v v out = 2.5v 14.5 output current (a) efficiency (%) load regulation, v out = 2.8 v 2.77 2.76 2.75 2.74 2.73 2.78 2.79 2.80 2.81 2.82 2.83 1 3 5 7 9 11 13 14.5 output current (a) v out (v) output voltage vs. output current, r sense = 6m 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 output current (a) output programming, vid4 = 0 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1.5 2.0 2.5 3.0 3.5 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 dac set point v out (v) v out (v) output programming, vid4 = 1 dac set point v out (v) 18 39 75 150 300 561 c ext (pf) oscillator frequency vs. c ext 50 250 450 650 850 1050 1250 frequency (khz)
rc5050 product specification 6 t ypical operating characteristics (contin ued) output ripple, 2.8v @ 13a time (2 s/division) cext pin v out (20mv/div) time (50 s/division) v out (50mv/div) transient response, 0.5a to 13a switching waveforms, 0.5a load time (2 s/division) 20mv/div 500mv/div 20mv/div 500mv/div time (2 s/division) switching waveforms, 13a load hdrv pin cext pin hidrv pin output startup, system power-up time (10ms/division) v in (1v/div ) v out (1v/div) time (10ms/division) enable (1v/div) v out (1v/div) output startup from re-enable 65-5050-04
product specification rc5050 7 t est cir cuit figure 1. 15a application circuit for pentium ii processor figure 2. output driver test circuit t ab le 2. recommended bulk capacitor s f or cpu-based applications application output current c in c out c out maxim um esr r sense motorola powerpc 603/604 motherboard 7a 2 x 1500 m f, 6v sanyo 6mv1500cx 2 x 1500 m f, 6v sanyo 6mv1500sx 22m w 10.5m w intel pentium ii klamath motherboard 14.2 3 x 1200 m f, 10v sayno 10mv1200eg 5 x 1500 m f, 6.3v sanyo 6mv1500gx 9.0m w 5.5m w intel pentium ii motherboard (all versions including next generation) 15a 3 x 1200 m f, 10v sayno 10mv1200eg 7 x 1500 m f, 6.3v sanyo 6mv1500gx 6.0m w 5.0m w vo gnd vid3 vid2 vid1 vid0 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 17 18 19 20 +5v pwrgd rc5050 vcc 65-5050-12 enable c10 0.1 f 0.1 f c11 10k c ext c7 0.1 f c6 1 f ds1 mbr2015ctl c in c5 0.1 f d1 1n4735a c12 1 f l1 1.3 h m1 irl3103 m2 irl3103 c8 0.1 f c9 0.1 f r sense * c out * l2 2.5 h vref c4 0.1 f +12v vid4 47 r5 r6 100pf *refer to table 2 for value of r sense , c out , and c in . +12v +5v 0.1 f 0.1 f 47 4.7 f vccqp vcca hidrv rise/fall hidrv 7000pf 1 f 90% 50% t r t f 10% 65-5050-11 90% 50% 10% rc5050 vccd gnda gndd gndp
rc5050 product specification 8 t ab le 3. rc5050 application bill of materials f or intel p entium ii pr ocessor s notes: 1. in order to meet the voltage transient requirements for the intel pentium ii motherboard application, the equivalent esr of the output capacitors must not exceed 7.5m w . in order to satisfy the specified output voltage regulation requirements for v out = 1.8v at 15a for next generation processors, the output capacitors must exhibit no more than 6.0m w equivalent esr for a motherboard application. the use of the capacitors recommended in table 1 will address this and other voltage specifications without significant added cost, although it is left up to the user to specify the components used. please refer to application bulletin 5 for additional considerations required to meet the intel pentium ii voltage transient specifications. 2. to optimize a converter for 15a at 1.8v output, f sw = 300 khz, change the value of l1 to 1.24 m h. 3. inductor l2 is recommended to isolate the 5v input supply from current surges caused by mosfet switching. l2 is not required for normal operation and may be omitted if desired. 4. for 15a designs using ir3103 mosfets, heat sinks with thermal resistance q sa < 50 c/w should be used. ref erence man ufacturer p ar t # description requirements/comments c4, c5, c7?11 panasonic ecu-v1h104zfx 0.1 m f 50v capacitor cext panasonic ecu-v1h121jcg 100pf capacitor c12, c6 panasonic ecsh1cy105r 1 m f 16v capacitor c in sanyo 10mv1200eg 1200 m f 10v electrolytic capacitor 10mm x 20mm esr < 62m w see table 2 c out sanyo 6mv1500gx 1500 m f 6.3v electrolytic capacitor 10mm x 20mm esr < 44m w see note 1 and table 2 ds1 motorola mbr2015ct schottky diode v f < 0.52 at i f = 10a d1 1n4735a 6.2v zener diode, motorola l1 skynet 320-8107 1.3 m h, 14a inductor dcr ~ 2.5m w see note 2 l2 skynet 320-6110 2.5 m h, 11a inductor dcr ~ 6m w see note 3 m1, m2 international rectifier irl3103 n-channel logic level enhancement mode mosfet r ds(on) < 19m w v gs < 4.5v, i d = 15a see note 4 r sense copel awg#18 5.5m w cuni alloy wire resistor r5 panasonic erj-6gey050y 47 w 5% resistor r6 panasonic erj-6enf10.0kv 10k w 5% resistor application inf ormation simple step-do wn con ver ter figure 3. simple buck dc-dc converter figure 3 illustrates a step-do wn dc-dc con v erter with no feedback control. the deri v ation of the basic step-do wn con v erter will serv e as a basis for the design equations for the rc5050. referring to figure 3, the basic operation be gins by closing the switch s1. when s1 is closed, the input v oltage v in is impressed across inductor l1. the current o wing in this inductor is gi v en by the follo wing equation: where t on is the duty c ycle (the time when s1 is closed). c1 r l vout + d1 v in 65-5050-06 l1 s1 i l v i n v o u t ( ) t o n l 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
product specification rc5050 9 when s1 opens, the diode d1 will conduct the inductor cur - rent and the output current will be deli v ered to the load according to the equation: where t s is the o v erall switching period and (t s ? t on ) is the time during which s1 is open. by solving these tw o equations, we can arri v e at the basic relationship for the output v oltage of a step-do wn con v erter: in order to obtain a more accurate approximation for v out , we must also include the forw ard v oltage v d across diode d1 and the switching loss, vsw . after taking into account these f actors, the ne w relationship becomes: where v sw = mosfet switching loss = i l ?r ds,on the rc5050 contr oller the rc5050 is a programmable dc-dc controller ic. when designed around the appropriate e xternal components, the rc5050 can be con gured to deli v er more than 14.5a of output current. the rc5050 utilizes both current-mode and v oltage-mode control to create an inte grated step-do wn v olt- age re gulator . during hea vy loading conditions, the rc5050 functions as a pwm step do wn re gulator . under light loads, the controller goes into pulse frequenc y modulation (pfm) or pulse-skipping mode. the controller will sense the load le v el and switch between the tw o modes automatically , thus optimizing its ef cienc y under all conditions. main contr ol loop f or this discussion, refer to the block diagram on page 1 of the data sheet. the control loop of the re gulator contains tw o main sections; the analog control block and the digital con- trol block. the analog block consists of signal conditioning ampli ers feeding into a set of comparators which pro vide the inputs to the digital block. the signal conditioning sec- tion accepts inputs from the ifb (current feedback) and vfb (v oltage feedback) pins and sets up tw o controlling signal paths. the v oltage control path ampli es the vfb signal and presents the output to one of the summing ampli er inputs. the current control path tak es the dif ference between the ifb and vfb pins and presents the resulting signal to another input of the summing ampli er . these tw o signals are then summed together with the slope compensation input from the oscillator . this output is then presented to a com- parator , which pro vides the main pwm control signal to the digital control block. the additional comparators in the analog control section set the point at which the max current comparator disables the output dri v e signals to the e xternal po wer mosfets. the digital control block is designed to tak e the comparator inputs along with the main clock signal from the oscillator and pro vide the appropriate pulses to the hidr v output pin that controls the e xternal po wer mosfet(s). the digital section w as designed utilizing high speed schottk y transistor logic, thus allo wing the rc5050 to operate at clock speeds as high as 1mhz. high current output driver s the rc5050 contains a high current output dri v er which uti- lizes high speed bipolar transistors arranged in a push-pull con guration. this dri v er is capable of deli v ering 1a of cur - rent in less than 100ns. the dri v er's po wer and ground are separated from the o v erall chip po wer and ground for addi- tional switching noise immunity . the output dri v er po wer supply , vccqp , is deri v ed from an e xternal 12v supply through a 47 w series resistor . the resulting v oltage is suf - cient to pro vide the g ate-source v oltage to the e xternal mos- fet required in order to achie v e a lo w r ds,on . internal v olta g e ref erence the reference included in the rc5050 is a precision band- g ap v oltage reference. the internal resistors are precisely trimmed to pro vide a near zero temperature coef cient (tc). added to the reference output is the resulting output from an inte grated 5-bit d a c. the d a c is pro vided in order to allo w the dc-dc con v erter output to be directly programmable via a 5-bit digital input. when the vid4 pin is in the high state, pins vid3?id0 will scale the output v oltage from 2v to 3.5v in 100mv increments. when the vid4 pin is pulled lo w , the output can be programmed from 1.3v to 2.05v in 50mv steps. f or guaranteed stable operation under all oper - ating conditions, a 0.1 m f decoupling capacitor should be connected to the vref pin. no load should be imposed upon this pin. p o wer good (pwrgd) the rc5050 po wer good function is designed in accordance with the pentium ii dc-dc con v erter speci cations and pro- vides a constant v oltage monitor on the vfb pin. the inter - nal circuitry compares the vfb signal to the vref v oltage and outputs an acti v e-lo w interrupt signal to the cpu should the po wer supply v oltage e xceed 10% of its nominal set- point. the po wer good ag pro vides no other control func- tion to the rc5050. output enab le (enable) intel speci cations state that the dc-dc con v erter should accept an open collector signal for controlling the output v oltage; a logic lo w on the en able pin disables the out- put v oltage. when disabled, the pwrgd output is in the lo w state. i l v o u t t s t o n ( ) l 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = v o u t v i n t o n t s - - - - - - - - - - - ? ? ? = v o u t v i n v d v s w + ( ) t o n t s - - - - - - - - - - - v d =
rc5050 product specification 10 upgrade present intel speci cations state that the dc-dc con v erter should accept an open collector signal (up#), used to indicate the presence of an upgrade processor . the typical state is high (standard processor). when in the lo w or ground state (ov erdri v e processor present), the output v oltage must be disabled unless the con v erter can supply the ov erdri v e pro- cessor's po wer requirements. because the rc5050 can sup- ply the ov erdri v e processor requirements, the up# signal is not required. over -v olta g e pr otection the rc5050 pro vides a constant monitor of the output v olt- age for protection ag ainst o v er v oltage conditions. if the v oltage at the vfb pin e xceeds 20% of the selected program v oltage, an o v er -v oltage condition will be assumed and the rc5050 will disable the output dri v e signal to the e xternal mosfet(s). shor t cir cuit pr otection a current sense methodology is implemented to disable the output dri v e signal to the mosfet(s) when an o v er -current condition is detected. the v oltage drop created by the output current o wing across a sense resistor is presented to an internal comparator . when the v oltage de v eloped across the sense resistor e xceeds the 120 mv comparator threshold v oltage, the rc5050 will reduce the output duty c ycle to pro- tect the po wer de vices. the dc-dc con v erter will return to normal operation after the f ault has been remo v ed, for either an o v er v oltage or a short circuit condition. oscillator the rc5050 oscillator section is implemented using a x ed current capacitor char ging con guration. an e xternal capaci- tor (c ext ) is used to preset the oscillator frequenc y between 80khz and 1mhz. this scheme allo ws maximum e xibility in setting the switching frequenc y as well as in choosing e xternal components. in general, a lo wer operating frequenc y will increase the peak ripple current o wing in the output inductor and thus require the use of a lar ger inductor v alue. operation at lo wer frequencies also increases the amount of ener gy storage that must be pro vided by the b ulk output capacitors during load transients due to the slo wer loop response of the controller . additionally , the ef cienc y losses due to switching of the mosfets will increase as the operating frequenc y is increased. therefore, ef cienc y will be optimized at lo wer operating frequencies. due to the trend of increasing load current at lo wer supply v oltages, an operating frequenc y of 300 khz has been cho- sen to optimize ef cienc y while maintaining e xcellent output re gulation and transient performance. design considerations and component selection mosfet selection this application requires the use of n-channel, logic le v el enhancement mode field ef fect t ransistors. desired characteristics are as follo ws: lo w static drain-source on-resistance, r ds,on < 37 m w (lo wer is better). lo w g ate dri v e v oltage, v gs 4.5v . po wer package with lo w thermal resistance. drain current rating of 20a minimum. drain-source v oltage > 15v the on-resistance (r ds,on ) is the primary parameter for mosfet selection. the on-resistance determines the po wer dissipation of the mosfet and therefore signi cantly af fects the ef cienc y of the dc-dc con v erter . t able 4 presents a list of suitable mosfets for this application. t w o mosfets in p arallel at higher load currents, it is recommend that tw o mosfets be used in parallel instead of a single mosfet . signi cant adv antages are realized using tw o mosfets in parallel: signi cant r eduction of po wer dissipation . maximum current of 15a with one mosfet : p mosfet = (i 2 r ds,on )(duty cycle) = (15) 2 (0.050 * )(2.8+0.4)/(5+0.4-0.35) = 7.1 w w ith tw o mosfets in parallel: p mosfet = (i 2 r ds,on )(duty cycle) = (15/2) 2 (0.037*)(2.8+0.4)/(5+0.4-0.35) = 1.3w/fet * note: r ds,on increases with temperature. assume r ds,on = 25m w at 25 c. r ds,on can easily increase to 50m w at high temperature when using a single mosfet . when using tw o mosfets in parallel, the temperature ef fects should not cause the r ds,on to rise abo v e the listed maximum v alue of 37m w . no added heat sink r equir ed. w ith po wer dissipation do wn to around one w att and with mosfets mounted at on the motherboard, no e xternal heat sink is required. the junction-to-case thermal resistance for the mosfet package (t o-220) is typically at 2 c/w and the motherboard serv es as an e xcellent heat sink. higher curr ent capability . w ith thermal management under control, this on-board dc-dc circuit is able to deli v er load currents up to 15a with no performance or reliability concerns.
product specification rc5050 11 mosfet gate bias figure 4 illustrates ho w an e xternal 12v supply is used to bias the output dri v er supply , vccqp . a 47 w resistor is used to limit the transient current into the vccqp pin and a 1 m f capacitor lter is used to lter the vccqp supply . this method pro vides a suf cient g ate-to-source bias v oltage (v gs ) to the mosfet , and therefore reduces the r ds,on and the resulting po wer loss within the mosfet . figure 5 illustrates ho w the r ds,on decreases dramatically as v gs increases. a 6.2v zener (d1) is used to clamp the v oltage at vccqp to a maximum of 12v , thus ensuring that the abso- lute maximum v oltage limit of the ic will not be e xceeded. figure 4. mosfet gate bias configuration pwm/pfm control 65-5050-07 +5v l1 vccqp hidrv m1 1 f rs ds1 d1 6.2v 47 cb vo +12v note: 1. r ds,on values at tj = 125 c for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only. t ab le 4. mosfet selection t ab le man ufacturer & model # conditions 1 r ds, on (m w ) p ac ka g e thermal resistance t yp. max. fuji 2sk1388 v gs =4v, i d =17.5a t j =25 c 25 37 t o-220 f ja =75 t j =125 c 37 siliconix si4410dy v gs =4.5v, i d =5a t j =25 c 16.5 20 so-8 (smd) f ja =50 t j =125 c 28 34 national semiconductor ndp706al v gs =5v, i d =40a t j =25 c 13 15 t o-220 f ja =62.5 f jc =1.5 ndp706ael t j =125 c 20 24 national semiconductor v gs =4.5v, i d =10a t j =25 c 31 40 t o-220 f ja =62.5 ndp603al t j =125 c 42 54 f jc =2.5 national semiconductor v gs =5v, i d =24a t j =25 c 22 25 t o-220 f ja =62.5 ndp606al t j =125 c 33 40 f jc =1.5 motorola v gs =5v, i d =37.5a t j =25 c 6 9 t o-263 f ja =62.5 mtb75n03hdl t j =125 c 9.3 14 (d 2 p ak) f jc =1.0 int. rectifier v gs =5v, i d =31a t j =25 c 28 t o-220 f ja =62.5 irlz44 t j =125 c 46 f jc =1.0 int. rectifier v gs =4.5v, i d =28a t j =25 c 19 t o-220 f ja =62.5 irl3103s t j =125 c 31 f jc =1.0
rc5050 product specification 12 figure 5. r ds,on vs. v gs for selected mosfets con ver ter ef cienc y losses due to parasitic resistance in the switches, inductor coil and sense resistor dominate at high load current le v els. the major loss mechanisms under hea vy loads, in usual order of importance, are: mosfet i 2 r losses inductor coil losses sense resistor losses gate-char ge losses diode-conduction losses t ransition losses input capacitor losses losses due to the operating supply current of the ic. the follo wing sections pro vide details of these dominant loss components. selecting the inductor the inductor is one of the most critical components to be selected in the dc-dc con v erter application.. the critical parameters are inductance (l), maximum dc current (io) and the dc coil resistance (r l ). the inductor core material is a crucial f actor in determining the amount of current the inductor will be able to withstand. as with all engineering designs, tradeof fs e xist between v arious types of core materi- als. in general, ferrites are popular due to their lo w cost, lo w emi properties and high frequenc y (>500khz) characteris- tics. molypermallo y po wder (mpp) materials e xhibit good saturation characteristics, lo w emi and lo w h ysteresis losses; ho we v er , the y tend to be e xpensi v e and more ef fec- ti v ely utilized at operating frequencies belo w 400khz. another critical parameter is the dc winding resistance of the inductor . this v alue should typically be reduced as much as possible, as the po wer loss in the dc resistance will de grade the ef cienc y of the con v erter by the relationship: p loss = i o 2 x r l . choosing the v alue of the inductor is a tradeof f between allo w able ripple v oltage and required transient response. the system designer can choose an y v alue within the allo wed range in order to maximize either ripple or transient perfor - mance. the rst order equation (close approximation) for minimum inductance is: where: v in = input po wer supply v out = output v oltage f = dc/dc con v erter switching frequenc y esr = equi v alent series resistance of all output capacitors in parallel v r = peak to peak output ripple v oltage b udget. the rst order equation for maximum allo wed inductance is: where: co = the total output capacitance i p = peak to peak load transient current v tb = the output v oltage tolerance b udget allocated to load transient d m = maximum duty c ycle for the dc/dc con v erter (usually 95%). some mar gin should be maintained between l min and l max . adding mar gin by increasing l max almost al w ays adds e xpense since all the v ariables are predetermined by system performance e xcept for c o , which must be increased to increase l max . adding mar gin by decreasing l min can either be done by purchasing capacitors with lo wer esr or by increasing the dc/dc con v erter switching frequenc y . the rc5050 is capable of running at high switching frequencies and pro vides signi cant cost sa vings for the ne wer cpu systems that typically run at high supply current. implementing shor t cir cuit pr otection intel currently requires all po wer supply manuf acturers to pro vide continuous protection ag ainst short circuit condi- tions that may damage the cpu. t o address this requirement, raytheon has implemented a current sense methodology to limit the po wer deli v ered to the load in the e v ent of an o v er - current condition. the v oltage drop created by the output current o wing across a sense resistor is presented to one terminal of an internal comparator with h ysterisis. the other comparator terminal has a threshold v oltage, nominally 120mv . t able 6 states the limits for the comparator threshold of the switching re gulator . 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1.5 2 2.5 3 3.5 4 5 6 7 8 9 10 11 gate-source voltage, v gs (v) r ds,on ( w ) fuji fuji 706a 706ael l m i n v o u t v i n ( ) f - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v o u t v i n - - - - - - - - - - - - - - - e s r v r - - - - - - - - - - - = l m i n 2 c o v i n v o u t ( ) d m v t b i p 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
product specification rc5050 13 t ab le 6. rc5050 shor t cir cuit comparator threshold v olta g e when designing the e xternal current sense circuitry , the designer must pay careful attention to the output limitations during normal operation and during a f ault condition. if the short circuit protection threshold current is set too lo w , the dc-dc con v erter may not be able to continuously deli v er the maximum cpu load current. if the threshold le v el is too high, the output dri v er may not be disabled at a safe limit and the resulting po wer dissipation within the mosfet(s) may rise to destructi v e le v els. the design equation used to set the short circuit threshold limit is as follo ws: where i pk and i min are peak ripple current and i load, max = maximum output load current the designer must also tak e into account the current (i pk ? min ), or the ripple current o wing through the induc- tor under normal operation. figure 6 illustrates the inductor current w a v eform for the rc5050 dc-dc con v erter at maximum load. figure 6. typical dc-dc converter inductor current waveform the calculation of this ripple current is as follo ws: where: v in = input v oltage to con v erter v sw = v oltage across the mosfet = i lo ad x r ds,on v d = f orw ard v oltage of the schottk y diode t = the switching period of the con v erter = 1/f s , where f s = switching frequenc y . f or an input v oltage of 5v , an output v oltage of 2.8v , an inductor v alue of 1.3 m h and a switching frequenc y of 285khz (using c ext = 100pf), the inductor current can be calculated as follo ws: therefore, for a continuous load current of 14.5a, the peak current through the inductor , i pk , is found to be: f or continuous operation at 14.5a, the short circuit detection threshold must be at least 17.5a. the ne xt step is to determine the v alue of the sense resistor . including tolerance, the sense resistor v alue can be approxi- mated as follo ws: where tf = t olerance f actor for the sense resistor . there are se v eral dif ferent types of sense resistors. t able 7 describes tolerance, size, po wer capability , temperature coef cient and cost of v arious sense resistors. shor t cir cuit comparator v threshold (mv) t ypical 120 minim um 100 maxim um 140 r s e n s e v t h i s c - - - - - - - - , where: i s c = output short circuit current = i s c i i n d u c t o r 3 i load, max i p k i m i n ( ) 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - + = t i t=1/f s t on t off i load, max (i pk -i min )/2 ipk imin i p k i m i n ( ) 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - v i n v s w v o u t ( ) l - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v o u t v d + ( ) v i n v s w v d + ( ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - t = i p k i m i n ( ) 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5.0 14.5 0.037 2.8 ( ) 1.3 10 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = 2.8 0.5 + ( ) 5.0 14.5 0.037 0.5 + ( ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 285 10 3 - - - - - - - - - - - - - - - - - - - - - - - 3 a ? i s c i i n d u c t o r 3 i load, max i p k i m i n ( ) 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + 14.5 3 + 17.5 a = = = r s e n s e v th,min i s c - - - - - - - - - - - - - - - - 1 t f ( ) v th,min 3.0 i load,max + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 t f ( ) = =
rc5050 product specification 14 based on the t olerance in the abo v e table: f or an embedded pc trace resistor and i l oad,max = 14.5a: f or a discrete resistor and i load, max = 14.5a: f or user con v enience, t able 8 lists the recommended v alues for sense resistor v alues at v arious load currents using an embedded pc trace resistor or discrete resistor . t ab le 8. r sense f or v arious load currents rc5050 shor t cir cuit current characteristics the rc5050 has a short circuit current characteristic that includes a foldback function with h ysteresis that pre v ents the dc-dc con v erter from oscillating in the e v ent of a short cir - cuit. a typical v -i characteristic of the dc-dc con v erter output using a sense resistor v alue of 6m w is presented in the t ypical operating characteristics section, page 5. the con- v erter performs with a typical v oltage re gulation characteris- tic until the v oltage across the resistor e xceeds the internal short circuit comparator threshold of 120mv . at this point, the internal comparator trips and sends a signal to the con- troller to turn of f the g ate dri v e to the po wer mosfet . this causes a drastic reduction in the output v oltage as the load re gulation collapses into the short circuit control mode. the output v oltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the dc-dc con v erter . sc hottky diode selection the application circuit of figure 1 sho ws a schottk y diode, ds1. ds1 is used as a yback diode to pro vide a constant current path for the inductor when m1 is turned of f. a vital selection criteria for ds1 is that it e xhibits a v ery lo w for - w ard v oltage drop, as this parameter will directly impact the re gulator ef cienc y as the output v oltage is reduced. t able 9 presents se v eral suitable schottk y diodes for this application. note that the diode mbr2015ctl has a v ery lo w forw ard v oltage drop. this diode is most ideal for applications where output v oltages belo w 2.8v are required. i load,max (a) r sense pc t race resistor (m w ) r sense discrete resistor (m w ) 10.0 5.5 7.3 11.2 5.0 6.7 12.4 4.6 6.2 13.9 4.2 5.6 14.0 4.2 5.6 14.5 4.1 5.4 r s e n s e v th,min 3.0 a i load, max + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 t f ( ) = = 100 m v 3.0 a 14.5 a + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 29 % ( ) 4.1 m w = r s e n s e v th,min 3.0 a i load, max + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 t f ( ) = = 100 m v 3.0 a 14.5 a + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 5 % ( ) 5.4 m w = t ab le 7. comparison of sense resistor s description motherboar d t race resistor discrete ir on allo y resistor (irc) discrete metal strip surface mount resistor (dale) discrete mncu allo y wire resistor discrete cuni allo y wire resistor (copel) tolerance factor (tf) 29% 5% ( 1% available) 1% 10% 10% size (l x w x h) 2" x 0.2" x 0.001" (1 oz cu trace) 0.45" x 0.065" x 0.200" 0.25" x 0.125" x 0.025" 0.200" x 0.04" x 0.160" 0.200" x 0.04" x 0.100" power capability >50a/in 1 watt (3w and 5w available) 1 watt 1 watt 1 watt temperature coefficient +4,000 ppm +30 ppm 75 ppm 30 ppm 20 ppm cost @10,000 piece low included in motherboard $0.31 $0.47 $0.09 $0.09
product specification rc5050 15 t ab le 9. sc hottky diode selection t ab le output filter capacitor s optimal ripple performance and transient response are func- tions of the lter capacitors used. since the 5v supply of a pc motherboard may be located se v eral inches a w ay from the dc-dc con v erter , input capacitance can play an impor - tant role in the load transient response of the rc5050. the higher the input capacitance, the more char ge storage is a v ailable for impro ving the current transfer through the fet(s). lo w ?sr?capacitors are best suited for this type of application and incorrect selection can in uence the con- v erter s o v erall performance. the input capacitor should be placed as close to the drain of the fet as possible to reduce the ef fect of ringing caused by long trace lengths. the esr rating of a capacitor is a dif cult number to quan- tify . esr or equi v alent series resistance, is de ned as the resonant impedance of the capacitor . since the capacitor is actually a comple x impedance de vice ha ving resistance, inductance and capacitance, it is quite natural for this de vice to ha v e a resonant frequenc y . as a rule, the lo wer the esr, the better suited the capacitor is for use in switching po wer supply applications. man y capacitor manuf acturers do not supply esr data. a useful estimate of the esr can be obtained using the follo wing equation: where: df is the dissipation f actor of the capacitor f is the operating frequenc y c is the capacitance in f arads. w ith this in mind, correct calculation of the output capaci- tance is crucial to the performance of the dc-dc con v erter . the output capacitor determines the o v erall loop stability , output v oltage ripple and load transient response. the calcu- lation is as follo ws: where: d v is the maximum v oltage de viation due to load transients d t is the reaction time of the po wer source (loop response time of the rc5050), approximately 2 m s i o is the output load current. f or i o = 12.2a (0.8 to 13a) and d v = 100mv , the b ulk capacitance required can be approximated as follo ws: input filter it is recommended that the design include an input inductor between the system +5v supply and the dc-dc con v erter input described belo w . this inductor will serv e to isolate the +5v supply from noise occurring in the switching portion of the dc-dc con v erter and also to limit the inrush current into the input capacitors during po wer up. an inductor v alue of around 2.5 m h is recommended, as illustrated belo w . pcb la y out guidelines and considerations pcb la y out guidelines 1. placement of the mosfets relati v e to the rc5050 is critical. the mosfets (m1 & m2), should be placed such that the trace length of the hidr v pin from the rc5050 to the fet g ates is minimized. a long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the lar ge g ate capacitance of the fet(s). this noise will radiate all o v er the board and will be v ery dif cult to suppress, especially when the oscillator frequenc y is increased. figure 7 depicts an e xample of proper placement of the mosfets in relation to the rc5050 as well as an e xample of incorrect placement of the mosfets. in general, all of the noisy switching lines should be k ept a w ay from the quiet analog section of the rc5050. that is to say , traces that connect to pins 12 and 13 (hidr v and vccqp) should be k ept f ar a w ay from the traces that connect to pins 1 through 5, and pin 16. man ufacturer model # conditions forwar d v olta g e v f philips pbyr1035 i f = 20a; t j =25 c i f = 20a; t j =125 c < 0.84v < 0.72v motorola mbr2035ct i f = 20a; t j =25 c i f = 20a; t j =125 c < 0.84v < 0.72v motorola mbr1545ct i f = 15a; t j =25 c i f = 15a; t j =125 c < 0.84v < 0.72v motorola mbr2015ctl i f = 20a; t j =25 c i f = 20a; t j =150 c < 0.58v < 0.48v e s r d f 2 p f c - - - - - - - - - - - - - = c m f ( ) i o d t d v i o e s r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = c m f ( ) i o d t d v i o e s r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12.2 2 m s 100 m v 12.2 a 7.5 m w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3200 m f = = = 1000 f, 10v electrolytic 0.1 f 65-5050-09 2.5 h 5v vin
rc5050 product specification 16 2. place decoupling capacitors (0.1 m f) as close to the rc5050 pins as possible. extra lead length on these capacitors will ne g ate their ability to suppress noise. 3. each vcc and gnd pin should ha v e its o wn via do wn to the appropriate plane underneath. this will help to add isolation between pins. 4. the cext timing capacitor should be surrounded with a ground trace if possible. the placement of a ground or po wer plane underneath the capacitor will also pro vide further noise isolation. this will help to shield the oscil- lator from the noise on the pcb. this capacitor should be placed as close to pin 1 as possible. 5. group the mosfets, inductor and schottk y as close together as possible for the same reasons as #1 abo v e. also place the input b ulk capacitors as close to the drains of mosfets as possible. in addition, placement of a 0.1 m f decoupling cap right on the drain of each mosfet will help to suppress some of the high frequenc y switching noise on the input of the dc-dc con v erter . 6. the traces that run from the rc5050 ifb (pin 4) and vfb (pin 5) pins should be run together ne xt to each other and be k elvin connected to the sense resistor . running these lines together will help in rejecting some of the common noise that is presented to the rc5050 feedback input. t ry as much as possible to run the noisy switching signals (hidr v & vccqp) on one layer and use the inner layers for po wer and ground only . if the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals vfb and ifb. pc boar d la y out chec klist bypass capacitor near vr ef pin. this pin should be adequately bypassed with a 0.1 m f capacitor . bypass capacitors f or vcc (5v). a 0.1 m f should be placed right ne xt to the vcc pin of the controller . bypass capacitors f or p o wer mosfet . a 0.1 m f cap should be placed at the drain connection of each po wer mosfet . 5v connection to the contr oller ic. each vcc pin on the ic should be connected to the 5v po wer plane through its o wn via. p o wer mosfet gate dri v e t race. the g ate dri v e trace should be routed on one layer only . the controller ic and the po wer fet should be oriented in such a w ay as to minimize the trace length of the g ate dri v e trace (< 1 inch). the g ate dri v e trace routing should stay a w ay from the quiet analog section of the rc50xx controller ic. (i.e. k eep a w ay from vref, ifb, vfb, and cext .) bulk capacitance. the input b ulk capacitance needs to be located less than 1" from the drain of the po wer mosfet . w e recommend the follo wing guidelines for the amount of b ulk input capacitance: ? f or an output load of <10a use 2 x 1500 m f caps. ? f or an output load of >10a use 3 x 1500 m f caps. the output b ulk capacitors should be located as close to the cpu sock et as possible. w e recommend the follo wing guidelines for the amount of b ulk output capacitance: ? f or pentium pro use 4 x 1500 m f . ? f or p55c mmx pentium/ amd k6 use 2x 1500 m f . ? f or pentium ii use 7 x 1500 m f . figure 7. examples of good and bad mosfet layout correct layout 8 7 6 2 11 15 14 13 12 3 16 1 5 4 poor layout rc5050 ?uiet" pins 65-5050-10 = 9 10 17 18 19 20 8 7 6 2 11 15 14 13 12 3 16 1 5 4 9 10 17 18 19 20 rc5050
product specification rc5050 17 inductor location. the inductor should be located near to the source of the po wer mosfet . the ideal condition w ould be to use an internal po wer plane to connect the source of the po wer mosfet , the inductor , and the yback schottk y diode together . sense resistor . the sense resistor should be located ne xt to the inductor . the tw o traces that run from the sense resistor to the rc50xx controller ic should be minimum width traces and be run parallel to each other . w e recommend these sense resistor v alues: ? f or pentium pro use 0.006 w . ? f or p55c mmx pentium/ amd k6 use 0.007 w . ? f or pentium ii use 0.006 w . gr ound plane. the rc50xx controller ic ha v e a continuous ground plane running underneath the entire chip area. each of the ic ground pins should ha v e a separate via connection do wn into the ground plane. input filter . in man y high current dc-dc con v erter designs, it is advisable to add an input inductor in order to create an input lter . an inductor on the order of 1-3uh is usually all that is required to perform the lter . when this component is added to the circuit, it is important that the rc50xx controller ic recei v e its vcc po wer from the system side of the input inductor and not the ?irty?side of the inductor . (ie the side that is connected to the po wer mosfet drains) t o minimize electr omagnetic interfer ence (emi). a v oid long ground connections. connect directly to the ground plane. use a star ground, where all grounds are connected to one point. use good quality inductors such as torrids or pot cores. a v oid rod inductors. route the high current carrying traces as po wer planes where possible. k eep sensiti v e lo w-le v el signals a w ay from the acti v e switching components. t ry to route them using the ground plane as a shield. example of a pc motherboar d la y out and gerber file a reference design for motherboard implementation of the rc5050 along with the layout gerber file and silk screen are presented belo w . the actual pcad gerber file can be obtained from a raytheon electronics local sales of ce or from mark eting at 650-966-7734. rc5050 ev aluation boar d raytheon electronics pro vides an e v aluation board for the purpose of v erifying the system le v el performance of the rc5050. the e v aluation board serv es as a guide as to what can be e xpected in performance with the supplied e xternal components and pcb layout. please call your local sales of ce or raytheon electronics mark eting department at 650-966-7734 for an e v aluation board.
rc5050 product specification 18
product specification rc5050 19 mec hanical dimensions ?20 lead soic a .093 .104 2.35 2.65 symbol inches min. max. min. max. millimeters notes a1 .004 .012 0.10 0.30 .020 0.51 b .013 0.33 c .009 .013 0.23 0.32 e .291 .299 7.40 7.60 e .394 .419 10.00 10.65 .010 .029 0.25 0.75 h .050 bsc 1.27 bsc h l .016 .050 0.40 1.27 0 8 0 8 3 6 5 2 2 n 20 20 a ccc .004 0.10 d .496 .512 12.60 13.00 notes: 1. 2. 3. 4. 5. 6. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals. 20 1 d a a1 ?c ccc c lead coplanarity seating plane e b l h x 45 c a 11 10 e h
rc5050 product specification 9/97 0.0m stock#ds30005050 raytheon company 1997 the information contained in this data sheet has been carefully compiled; ho we v er , it shall not by implication or otherwise become part of the terms and conditions of an y subsequent sale. raytheon s liability shall be determined solely by its standard terms and conditions of sale. no representation as to application or use or that the circuits are either licensed or free from patent infringement is intende d or implied. raytheon reserv es the right to change the circuitry and an y other data at an y time without notice and assumes no liability for errors. life support policy: raytheon s products are not designed for use in life support applications, wherein a f ailure or malfunction of the component can reasonably be e xpected to result in personal injury . the user of raytheon components in life support applications assumes all risk of such use and indemni es raytheon compan y ag ainst all damages. raytheon electronics semiconductor division 350 ellis street mountain view, ca 94043 650.968.9211 fax 650.966.7742 or dering inf ormation pr oduct number p ac ka g e RC5050M 20 pin soic

▲Up To Search▲

Price & Availability of RC5050M

	To Download RC5050M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .